SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2023

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QF_UFDTLIRA (Proof Exhibition Track)

Competition results for the QF_UFDTLIRA logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 66
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5 0 66 2.807 2.73600 0
cvc5-lfsc 0 66 3.13 3.0600 0
SMTInterpol 0 66 76.289 50.70600 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5 0 662.8072.73600 0
cvc5-lfsc 0 663.133.0600 0
SMTInterpol 0 6676.28950.70600 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.