The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_RDL logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 113 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
SMTInterpol | 0 | 79 | 8236.947 | 6499.19 | 34 | 34 | 0 |
cvc5-lfsc | 0 | 64 | 6896.657 | 6894.564 | 49 | 49 | 0 |
cvc5 | 0 | 7 | 322.411 | 318.963 | 106 | 102 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
SMTInterpol | 0 | 79 | 8236.947 | 6499.19 | 34 | 34 | 0 |
cvc5-lfsc | 0 | 64 | 6896.657 | 6894.564 | 49 | 49 | 0 |
cvc5 | 0 | 7 | 322.411 | 318.963 | 106 | 102 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.