SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2023

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Model Validation Track
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QF_RDL (Proof Exhibition Track)

Competition results for the QF_RDL logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 113
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
SMTInterpol 0 79 8236.947 6499.193434 0
cvc5-lfsc 0 64 6896.657 6894.5644949 0
cvc5 0 7 322.411 318.963106102 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
SMTInterpol 0 798236.9476499.193434 0
cvc5-lfsc 0 646896.6576894.5644949 0
cvc5 0 7322.411318.963106102 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.