SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2023

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Model Validation Track
Proof Exhibition Track
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QF_IDL (Proof Exhibition Track)

Competition results for the QF_IDL logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 229
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
SMTInterpol 0 143 19691.751 16307.3738690 0
cvc5-lfsc 0 143 21574.152 21508.2028686 0
cvc5 0 22 577.342 572.525207205 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
SMTInterpol 0 14320282.16115430.4458686 0
cvc5-lfsc 0 14321574.15221508.2028686 0
cvc5 0 22577.342572.525207205 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.