The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the QF_IDL logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 229 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
SMTInterpol | 0 | 143 | 19691.751 | 16307.373 | 86 | 90 | 0 |
cvc5-lfsc | 0 | 143 | 21574.152 | 21508.202 | 86 | 86 | 0 |
cvc5 | 0 | 22 | 577.342 | 572.525 | 207 | 205 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
SMTInterpol | 0 | 143 | 20282.161 | 15430.445 | 86 | 86 | 0 |
cvc5-lfsc | 0 | 143 | 21574.152 | 21508.202 | 86 | 86 | 0 |
cvc5 | 0 | 22 | 577.342 | 572.525 | 207 | 205 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.