The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_DT logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 1130 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
SMTInterpol | 0 | 1095 | 3601.604 | 2476.033 | 35 | 35 | 0 |
cvc5-lfsc | 0 | 1092 | 50.012 | 48.97 | 38 | 38 | 0 |
cvc5 | 0 | 1092 | 52.622 | 51.047 | 38 | 38 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
SMTInterpol | 0 | 1095 | 3601.604 | 2476.033 | 35 | 35 | 0 |
cvc5-lfsc | 0 | 1092 | 50.012 | 48.97 | 38 | 38 | 0 |
cvc5 | 0 | 1092 | 52.622 | 51.047 | 38 | 38 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.