The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_DT logic in the Model Validation Track.
Page generated on 2023-07-06 16:06:00 +0000
Benchmarks: 1836 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
SMTInterpol | SMTInterpol |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
SMTInterpol | 0 | 1792 | 2854.132 | 2418.055 | 43 | 0 |
cvc5 | 0 | 1198 | 5432.684 | 5433.687 | 39 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
SMTInterpol | 0 | 1792 | 2854.132 | 2418.055 | 43 | 0 |
cvc5 | 0 | 1198 | 5432.684 | 5433.687 | 39 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.