SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions

SMT-COMP 2023

Rules
Benchmarks
Specs
Model Validation Track
Proof Exhibition Track
Parallel & Cloud Tracks
Participants
Results
Statistics
Comparisons
Slides

BVFPLRA (Unsat Core Track)

Competition results for the BVFPLRA logic in the Unsat Core Track.

Page generated on 2023-07-06 16:05:43 +0000

Benchmarks: 11
Time Limit: 1200 seconds
Memory Limit: 60 GB

Winners

Sequential PerformanceParallel Performance
BitwuzlaBitwuzla

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreTimeout Memout
Bitwuzla Fixedn 0 50 4.094 4.0940 0
Bitwuzla 0 50 4.115 4.1160 0
2020-CVC4-ucn 0 50 11.548 11.5470 0
cvc5 0 29 30.52 30.5180 0
UltimateEliminator+MathSAT 0 0 0.0 0.00 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreTimeout Memout
Bitwuzla Fixedn 0 504.0944.0940 0
Bitwuzla 0 504.1154.1160 0
2020-CVC4-ucn 0 5011.54811.5470 0
cvc5 0 2930.5230.5180 0
UltimateEliminator+MathSAT 0 00.00.00 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.