The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the BV logic in the Unsat Core Track.
Page generated on 2023-07-06 16:05:43 +0000
Benchmarks: 425 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5 | cvc5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 91 | 958.526 | 954.336 | 88 | 0 |
cvc5 | 0 | 81 | 1167.709 | 1166.672 | 88 | 0 |
Bitwuzla | 0 | 36 | 3295.393 | 3296.124 | 150 | 0 |
Bitwuzla Fixedn | 0 | 36 | 3466.606 | 3461.943 | 150 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 6.72 | 3.408 | 0 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2020-CVC4-ucn | 0 | 91 | 958.526 | 954.336 | 88 | 0 |
cvc5 | 0 | 81 | 1167.709 | 1166.672 | 88 | 0 |
Bitwuzla | 0 | 36 | 3295.393 | 3296.124 | 150 | 0 |
Bitwuzla Fixedn | 0 | 36 | 3466.606 | 3461.943 | 150 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 6.72 | 3.408 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.