The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFDTLIRA logic in the Unsat Core Track.
Page generated on 2023-07-06 16:05:43 +0000
Benchmarks: 4986 Time Limit: 1200 seconds Memory Limit: 60 GB
| Sequential Performance | Parallel Performance |
|---|---|
| cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2021-cvc5-ucn | 0 | 187569 | 2318.721 | 2317.622 | 24 | 0 |
| cvc5 | 0 | 184428 | 2118.473 | 2116.631 | 40 | 0 |
| SMTInterpol | 0 | 162742 | 30919.836 | 19247.193 | 669 | 0 |
| Vampire | 0 | 17222 | 1187.128 | 330.122 | 338 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2021-cvc5-ucn | 0 | 187569 | 2318.721 | 2317.622 | 24 | 0 |
| cvc5 | 0 | 184428 | 2118.473 | 2116.631 | 40 | 0 |
| SMTInterpol | 0 | 162742 | 30919.836 | 19247.193 | 665 | 0 |
| Vampire | 0 | 17222 | 1187.128 | 330.122 | 237 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.