The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFDTLIA logic in the Unsat Core Track.
Page generated on 2023-07-06 16:05:43 +0000
Benchmarks: 88 Time Limit: 1200 seconds Memory Limit: 60 GB
| Sequential Performance | Parallel Performance |
|---|---|
| SMTInterpol | SMTInterpol |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2021-cvc5-ucn | 0 | 61663 | 171.642 | 167.128 | 1 | 0 |
| SMTInterpol | 0 | 61652 | 2060.815 | 1376.981 | 0 | 0 |
| Vampire | 0 | 60772 | 4567.575 | 1162.775 | 0 | 0 |
| cvc5 | 0 | 1342 | 187.69 | 187.676 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2021-cvc5-ucn | 0 | 61663 | 171.642 | 167.128 | 1 | 0 |
| SMTInterpol | 0 | 61652 | 2060.815 | 1376.981 | 0 | 0 |
| Vampire | 0 | 60772 | 4567.575 | 1162.775 | 0 | 0 |
| cvc5 | 0 | 1342 | 187.69 | 187.676 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.