The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the UFFPDTNIRA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 321 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 176 | 159639.626 | 159661.254 | 145 | 131 | 2 |
cvc5 | 0 | 176 | 170468.567 | 170494.899 | 145 | 140 | 2 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 176 | 159656.546 | 159656.414 | 145 | 131 | 2 |
cvc5 | 0 | 176 | 170490.677 | 170487.639 | 145 | 140 | 2 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.