The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFDTNIRA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 2012 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 2004 | 6752.303 | 6750.367 | 8 | 5 | 0 |
cvc5 | 0 | 1986 | 23104.092 | 22706.093 | 26 | 11 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 2004 | 6754.073 | 6750.097 | 8 | 5 | 0 |
cvc5 | 0 | 1986 | 23106.482 | 22705.553 | 26 | 11 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.