SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2022

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UFDTNIRA (Proof Exhibition Track)

Competition results for the UFDTNIRA logic in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 2012
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 2004 6752.303 6750.36785 0
cvc5 0 1986 23104.092 22706.0932611 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 20046754.0736750.09785 0
cvc5 0 198623106.48222705.5532611 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.