SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2022

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UFBVLIA (Proof Exhibition Track)

Competition results for the UFBVLIA logic in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 8
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5 0 0 0.937 0.93280 0
cvc5-lfsc 0 0 0.94 0.93580 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5 0 00.9370.93280 0
cvc5-lfsc 0 00.940.93580 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.