The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFBV logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 126 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 58 | 28437.659 | 28440.287 | 68 | 17 | 3 |
cvc5 | 0 | 27 | 56999.557 | 56963.995 | 99 | 40 | 3 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 58 | 28439.229 | 28439.547 | 68 | 17 | 3 |
cvc5 | 0 | 27 | 57005.667 | 56962.115 | 99 | 40 | 3 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.