The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_Equality+Bitvec division in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 2725 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics: This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 2305 | 598913.122 | 598811.462 | 420 | 0 | 415 | 5 |
cvc5 | 0 | 1614 | 1297944.52 | 1297872.301 | 1111 | 0 | 1057 | 5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 2305 | 599032.772 | 598795.122 | 420 | 0 | 415 | 5 |
cvc5 | 0 | 1614 | 1298135.49 | 1297819.701 | 1111 | 0 | 1057 | 5 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.