The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_Bitvec division in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 13848 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics:
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 6516 | 9227575.117 | 9228353.093 | 7332 | 0 | 7271 | 52 |
cvc5 | 0 | 4140 | 11348618.222 | 11347583.394 | 9708 | 0 | 9177 | 54 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 6516 | 9228659.117 | 9228125.263 | 7332 | 0 | 7270 | 52 |
cvc5 | 0 | 4140 | 11350385.442 | 11347119.994 | 9708 | 0 | 9177 | 54 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.