The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the BVFPLRA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 9 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 0 | 10798.66 | 10800.53 | 9 | 9 | 0 |
| cvc5-lfsc | 0 | 0 | 10798.67 | 10800.39 | 9 | 9 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 0 | 10800.0 | 10800.0 | 9 | 9 | 0 |
| cvc5-lfsc | 0 | 0 | 10800.0 | 10800.0 | 9 | 9 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.