The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFNIRA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 549 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 519 | 36681.944 | 36689.608 | 30 | 29 | 0 |
cvc5-lfsc | 0 | 519 | 37457.248 | 37472.255 | 30 | 30 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 519 | 36693.094 | 36687.768 | 30 | 29 | 0 |
cvc5-lfsc | 0 | 519 | 37470.258 | 37470.745 | 30 | 30 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.