SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2022

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Proof Exhibition Track
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AUFBVDTNIRA (Proof Exhibition Track)

Competition results for the AUFBVDTNIRA logic in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 1062
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 129 1114396.028 1114486.244933296 631
cvc5 0 17 1242839.83 1242881.4011045365 663

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 1291114484.7181114469.594933296 631
cvc5 0 171242932.841242861.7211045365 663

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.