The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFBVDTNIRA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 1062 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 129 | 1114396.028 | 1114486.244 | 933 | 296 | 631 |
cvc5 | 0 | 17 | 1242839.83 | 1242881.401 | 1045 | 365 | 663 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 129 | 1114484.718 | 1114469.594 | 933 | 296 | 631 |
cvc5 | 0 | 17 | 1242932.84 | 1242861.721 | 1045 | 365 | 663 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.