The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFBVDTLIA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 171 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 112 | 70839.772 | 70872.187 | 59 | 58 | 1 |
cvc5 | 0 | 98 | 86290.235 | 86303.191 | 73 | 70 | 1 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 112 | 70869.262 | 70869.297 | 59 | 58 | 1 |
cvc5 | 0 | 98 | 86321.855 | 86299.731 | 73 | 70 | 1 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.