The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UFIDL logic in the Model Validation Track.
Page generated on 2021-07-18 17:31:50 +0000
Benchmarks: 206 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
SMTInterpol | SMTInterpol |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
SMTInterpol | 0 | 198 | 21701.718 | 20263.947 | 8 | 0 |
z3-mvn | 0 | 177 | 38017.127 | 37990.902 | 29 | 0 |
cvc5-mv | 0 | 167 | 70806.017 | 70821.869 | 39 | 0 |
Yices2 model-validation | 0 | 140 | 93215.242 | 93226.918 | 66 | 0 |
MathSAT5n | 0 | 106 | 120018.61 | 120045.007 | 100 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
SMTInterpol | 0 | 199 | 21714.748 | 20259.337 | 7 | 0 |
z3-mvn | 0 | 177 | 38020.197 | 37989.572 | 29 | 0 |
cvc5-mv | 0 | 167 | 70814.497 | 70819.919 | 39 | 0 |
Yices2 model-validation | 0 | 140 | 93222.492 | 93224.738 | 66 | 0 |
MathSAT5n | 0 | 106 | 120040.64 | 120040.647 | 100 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.