The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UFDTLIRA logic in the Unsat Core Track.
Page generated on 2021-07-18 17:31:25 +0000
Benchmarks: 17 Time Limit: 1200 seconds Memory Limit: 60 GB
| Sequential Performance | Parallel Performance |
|---|---|
| cvc5-uc | cvc5-uc |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| cvc5-uc | 0 | 162 | 0.365 | 0.357 | 0 | 0 |
| SMTInterpol | 0 | 94 | 7.528 | 5.462 | 0 | 0 |
| SMTInterpol-remus | 0 | 0 | 4.259 | 3.428 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| cvc5-uc | 0 | 162 | 0.365 | 0.357 | 0 | 0 |
| SMTInterpol | 0 | 94 | 7.528 | 5.462 | 0 | 0 |
| SMTInterpol-remus | 0 | 0 | 4.259 | 3.428 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.