The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UFDT logic in the Unsat Core Track.
Page generated on 2021-07-18 17:31:25 +0000
Benchmarks: 100 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5-uc | cvc5-uc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
z3n | 0 | 684213 | 46700.039 | 46718.909 | 22 | 0 |
cvc5-uc | 0 | 109799 | 108628.462 | 108643.988 | 81 | 0 |
SMTInterpol | 0 | 40104 | 109555.819 | 108846.338 | 84 | 0 |
SMTInterpol-remus | 0 | 40104 | 110605.763 | 109774.909 | 84 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
z3n | 0 | 684213 | 46709.509 | 46717.939 | 22 | 0 |
cvc5-uc | 0 | 109799 | 108639.362 | 108641.058 | 81 | 0 |
SMTInterpol | 0 | 46404 | 109851.649 | 108788.708 | 81 | 0 |
SMTInterpol-remus | 0 | 41621 | 110810.093 | 109694.589 | 82 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.