SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2021

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QF_RDL (Model Validation Track)

Competition results for the QF_RDL logic in the Model Validation Track.

Page generated on 2021-07-18 17:31:50 +0000

Benchmarks: 109
Time Limit: 1200 seconds
Memory Limit: 60 GB

Winners

Sequential PerformanceParallel Performance
Yices2 model-validationYices2 model-validation

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreTimeout Memout
Yices2 model-validation 0 109 802.954 801.5410 0
2020-Yices2-fixed Model Validationn 0 109 804.947 804.0150 0
cvc5-mv 0 107 6281.64 6282.8552 0
MathSAT5n 0 107 6776.05 6777.1432 0
z3-mvn 0 104 10782.636 10780.195 0
SMTInterpol 0 103 14173.804 13142.9626 0
OpenSMT 0 100 16171.735 16173.7839 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreTimeout Memout
Yices2 model-validation 0 109802.954801.5410 0
2020-Yices2-fixed Model Validationn 0 109804.947804.0150 0
cvc5-mv 0 1076281.826282.7352 0
MathSAT5n 0 1076776.326777.0032 0
z3-mvn 0 10410783.00610779.915 0
SMTInterpol 0 10314173.80413142.9626 0
OpenSMT 0 10016172.25516173.4839 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.