The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_RDL logic in the Model Validation Track.
Page generated on 2021-07-18 17:31:50 +0000
Benchmarks: 109 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
Yices2 model-validation | Yices2 model-validation |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Yices2 model-validation | 0 | 109 | 802.954 | 801.541 | 0 | 0 |
2020-Yices2-fixed Model Validationn | 0 | 109 | 804.947 | 804.015 | 0 | 0 |
cvc5-mv | 0 | 107 | 6281.64 | 6282.855 | 2 | 0 |
MathSAT5n | 0 | 107 | 6776.05 | 6777.143 | 2 | 0 |
z3-mvn | 0 | 104 | 10782.636 | 10780.19 | 5 | 0 |
SMTInterpol | 0 | 103 | 14173.804 | 13142.962 | 6 | 0 |
OpenSMT | 0 | 100 | 16171.735 | 16173.783 | 9 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Yices2 model-validation | 0 | 109 | 802.954 | 801.541 | 0 | 0 |
2020-Yices2-fixed Model Validationn | 0 | 109 | 804.947 | 804.015 | 0 | 0 |
cvc5-mv | 0 | 107 | 6281.82 | 6282.735 | 2 | 0 |
MathSAT5n | 0 | 107 | 6776.32 | 6777.003 | 2 | 0 |
z3-mvn | 0 | 104 | 10783.006 | 10779.91 | 5 | 0 |
SMTInterpol | 0 | 103 | 14173.804 | 13142.962 | 6 | 0 |
OpenSMT | 0 | 100 | 16172.255 | 16173.483 | 9 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.