The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_DT logic in the Unsat Core Track.
Page generated on 2021-07-18 17:31:25 +0000
Benchmarks: 100 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
SMTInterpol | SMTInterpol |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
z3n | 0 | 182036 | 100899.378 | 100939.017 | 76 | 0 |
SMTInterpol | 0 | 108156 | 111689.04 | 110845.49 | 84 | 0 |
SMTInterpol-remus | 0 | 108156 | 112731.832 | 111742.888 | 84 | 0 |
cvc5-uc | 0 | 68043 | 112160.661 | 112179.13 | 88 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
z3n | 0 | 182036 | 100930.518 | 100935.157 | 76 | 0 |
SMTInterpol | 0 | 114815 | 111802.89 | 110720.12 | 82 | 0 |
SMTInterpol-remus | 0 | 114815 | 112854.142 | 111636.178 | 82 | 0 |
cvc5-uc | 0 | 68043 | 112175.591 | 112176.03 | 88 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.