The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the BV logic in the Incremental Track.
Page generated on 2021-07-18 17:30:28 +0000
Benchmarks: 18 Time Limit: 1200 seconds Memory Limit: 60 GB
Parallel Performance |
---|
cvc5-inc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
2019-Z3n | 0 | 37195 | 7600.574 | 7599.681 | 1661 | 6 | 0 |
z3n | 0 | 37034 | 6442.788 | 6441.705 | 1822 | 5 | 0 |
cvc5-inc | 0 | 35849 | 9349.404 | 9347.949 | 3007 | 7 | 0 |
UltimateEliminator+MathSAT | 0 | 18912 | 1547.821 | 1391.669 | 19944 | 1 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.