The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the LRA division in the Incremental Track.
Page generated on 2019-07-23 17:57:24 +0000
Benchmarks: 5 Time Limit: 2400 seconds Memory Limit: 60 GB
| Parallel Performance |
|---|
| — |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|
| CVC4-inc | 0 | 0 | 0.03 | 0.043 | 15969 | 0 | 0 | |
| Z3n | 0 | 0 | 0.169 | 0.168 | 15969 | 0 | 0 | |
| SMTInterpol | 0 | 0 | 1.016 | 0.886 | 15969 | 0 | 0 | |
| UltimateEliminator+SMTInterpol | 0 | 0 | 15.172 | 9.788 | 15969 | 0 | 0 | |
| UltimateEliminator+MathSAT-5.5.4 | 0 | 0 | 15.339 | 10.952 | 15969 | 0 | 0 | |
| UltimateEliminator+Yices-2.6.1 | 0 | 0 | 15.719 | 11.028 | 15969 | 0 | 0 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.