The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the LIA division in the Unsat Core Track.
Page generated on 2019-07-23 17:57:45 +0000
Benchmarks: 200 Time Limit: 2400 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
CVC4-uc | CVC4-uc |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|
2018-Z3 (unsat core)n | 0 | 12 | 10.211 | 10.225 | 0 | 0 | |
Z3n | 0 | 11 | 10.381 | 10.386 | 0 | 0 | |
CVC4-uc | 0 | 8 | 9.468 | 9.466 | 0 | 0 | |
UltimateEliminator+MathSAT-5.5.4 | 0 | 1 | 78056.111 | 77708.419 | 32 | 0 | |
UltimateEliminator+SMTInterpol | 0 | 1 | 78669.958 | 78307.86 | 32 | 0 | |
UltimateEliminator+Yices-2.6.1 | 0 | 0 | 27460.474 | 27177.119 | 11 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|
2018-Z3 (unsat core)n | 0 | 12 | 10.211 | 10.225 | 0 | 0 | |
Z3n | 0 | 11 | 10.381 | 10.386 | 0 | 0 | |
CVC4-uc | 0 | 8 | 9.468 | 9.466 | 0 | 0 | |
UltimateEliminator+MathSAT-5.5.4 | 0 | 1 | 78056.111 | 77708.419 | 32 | 0 | |
UltimateEliminator+SMTInterpol | 0 | 1 | 78669.958 | 78307.86 | 32 | 0 | |
UltimateEliminator+Yices-2.6.1 | 0 | 0 | 27460.474 | 27177.119 | 11 | 0 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.