The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFLRA logic in the Incremental Track. Chart
Results were generated on 2026-07-25
Benchmarks: 587
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 90804 | 14783.35 | 14783.35 | 0 | 587 | 0 | 4 | 0 |
| SMTInterpol | 0 | 73888 | 212324.56 | 212324.56 | 0 | 587 | 0 | 135 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 3.52 | 4.49 | 0 | 587 | 0 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 2047.88 | 768.39 | 0 | 587 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 587 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 82332 | 1302.49 | 1302.49 | 0 | 495 | 92 | 0 | 0 |
| SMTInterpol | 0 | 18090 | 735.41 | 735.41 | 0 | 242 | 345 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 3.52 | 4.49 | 0 | 587 | 0 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 2047.88 | 768.39 | 0 | 587 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 587 | 0 | 0 | 0 |