The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFDTNIRA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 806
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 745 | 537.55 | 631.31 | 745 | 0 | 745 | 61 | 0 | 16 | 0 |
| cvc5-cvc5-xyz ne | 0 | 745 (base +0) | 546.51 | 638.37 | 745 | 0 | 745 | 61 | 0 | 16 | 0 |
| z3-BooledASS ne | 0 | 718 (base -2) | 132.97 | 221.29 | 718 | 10 | 708 | 88 | 0 | 88 | 0 |
| SMTInterpol | 0 | 555 | 7483.83 | 5571.01 | 555 | 0 | 555 | 251 | 0 | 153 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 745 | 541.95 | 633.76 | 745 | 0 | 745 | 61 | 0 | 16 | 0 |
| z3-BooledASS-base n | 0 | 720 | 453.90 | 542.27 | 720 | 10 | 710 | 86 | 0 | 86 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 745 | 537.55 | 631.31 | 745 | 0 | 745 | 61 | 0 | 16 | 0 |
| cvc5-cvc5-xyz ne | 0 | 745 (base +0) | 546.51 | 638.37 | 745 | 0 | 745 | 61 | 0 | 16 | 0 |
| z3-BooledASS ne | 0 | 718 (base -2) | 132.97 | 221.29 | 718 | 10 | 708 | 88 | 0 | 88 | 0 |
| SMTInterpol | 0 | 555 | 7483.83 | 5571.01 | 555 | 0 | 555 | 251 | 0 | 153 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 745 | 541.95 | 633.76 | 745 | 0 | 745 | 61 | 0 | 16 | 0 |
| z3-BooledASS-base n | 0 | 720 | 453.90 | 542.27 | 720 | 10 | 710 | 86 | 0 | 86 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 10 (base +0) | 1.72 | 2.95 | 10 | 10 | 0 | 0 | 796 | 0 | 0 |
| SMTInterpol | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 10 | 796 | 0 | 0 |
| cvc5 | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 10 | 796 | 2 | 0 |
| cvc5-cvc5-xyz ne | 0 | 0 (base +0) | 0.00 | 0.00 | 0 | 0 | 0 | 10 | 796 | 2 | 0 |
| z3-BooledASS-base n | 0 | 10 | 1.69 | 2.91 | 10 | 10 | 0 | 0 | 796 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 10 | 796 | 2 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 745 | 537.55 | 631.31 | 745 | 0 | 745 | 2 | 59 | 2 | 0 |
| cvc5-cvc5-xyz ne | 0 | 745 (base +0) | 546.51 | 638.37 | 745 | 0 | 745 | 2 | 59 | 2 | 0 |
| z3-BooledASS ne | 0 | 708 (base -2) | 131.24 | 218.34 | 708 | 0 | 708 | 39 | 59 | 39 | 0 |
| SMTInterpol | 0 | 555 | 7483.83 | 5571.01 | 555 | 0 | 555 | 192 | 59 | 105 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 745 | 541.95 | 633.76 | 745 | 0 | 745 | 2 | 59 | 2 | 0 |
| z3-BooledASS-base n | 0 | 710 | 452.21 | 539.36 | 710 | 0 | 710 | 37 | 59 | 37 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 744 | 155.16 | 248.75 | 744 | 0 | 744 | 45 | 17 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 744 (base +0) | 158.64 | 250.35 | 744 | 0 | 744 | 45 | 17 | 0 | 0 |
| z3-BooledASS ne | 0 | 718 (base -1) | 132.97 | 221.29 | 718 | 10 | 708 | 0 | 88 | 0 | 0 |
| SMTInterpol | 0 | 539 | 1692.91 | 706.18 | 539 | 0 | 539 | 32 | 235 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 744 | 158.59 | 250.25 | 744 | 0 | 744 | 45 | 17 | 0 | 0 |
| z3-BooledASS-base n | 0 | 719 | 135.34 | 223.57 | 719 | 10 | 709 | 0 | 87 | 0 | 0 |