The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFDTNIA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 500
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 469 (base -5) | 2215.63 | 2273.10 | 469 | 0 | 469 | 31 | 0 | 30 | 0 |
| cvc5 | 0 | 452 | 20178.76 | 20237.49 | 452 | 0 | 452 | 48 | 0 | 48 | 0 |
| cvc5-cvc5-xyz ne | 0 | 451 (base +0) | 19747.83 | 19805.49 | 451 | 0 | 451 | 49 | 0 | 49 | 0 |
| SMTInterpol | 0 | 53 | 1275.54 | 632.04 | 53 | 0 | 53 | 447 | 0 | 239 | 0 |
| z3-BooledASS-base n | 0 | 474 | 2831.48 | 2889.53 | 474 | 0 | 474 | 26 | 0 | 25 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 451 | 19704.29 | 19762.18 | 451 | 0 | 451 | 49 | 0 | 49 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 469 (base -5) | 2215.63 | 2273.10 | 469 | 0 | 469 | 31 | 0 | 30 | 0 |
| cvc5 | 0 | 452 | 20178.76 | 20237.49 | 452 | 0 | 452 | 48 | 0 | 48 | 0 |
| cvc5-cvc5-xyz ne | 0 | 451 (base +0) | 19747.83 | 19805.49 | 451 | 0 | 451 | 49 | 0 | 49 | 0 |
| SMTInterpol | 0 | 53 | 1275.54 | 632.04 | 53 | 0 | 53 | 447 | 0 | 239 | 0 |
| z3-BooledASS-base n | 0 | 474 | 2831.48 | 2889.53 | 474 | 0 | 474 | 26 | 0 | 25 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 451 | 19704.29 | 19762.18 | 451 | 0 | 451 | 49 | 0 | 49 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 469 (base -5) | 2215.63 | 2273.10 | 469 | 0 | 469 | 31 | 0 | 30 | 0 |
| cvc5 | 0 | 452 | 20178.76 | 20237.49 | 452 | 0 | 452 | 48 | 0 | 48 | 0 |
| cvc5-cvc5-xyz ne | 0 | 451 (base +0) | 19747.83 | 19805.49 | 451 | 0 | 451 | 49 | 0 | 49 | 0 |
| SMTInterpol | 0 | 53 | 1275.54 | 632.04 | 53 | 0 | 53 | 447 | 0 | 239 | 0 |
| z3-BooledASS-base n | 0 | 474 | 2831.48 | 2889.53 | 474 | 0 | 474 | 26 | 0 | 25 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 451 | 19704.29 | 19762.18 | 451 | 0 | 451 | 49 | 0 | 49 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 457 (base +0) | 462.85 | 518.67 | 457 | 0 | 457 | 0 | 43 | 0 | 0 |
| cvc5 | 0 | 345 | 1544.23 | 1587.48 | 345 | 0 | 345 | 0 | 155 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 344 (base -1) | 1535.90 | 1578.39 | 344 | 0 | 344 | 0 | 156 | 0 | 0 |
| SMTInterpol | 0 | 49 | 900.92 | 381.66 | 49 | 0 | 49 | 0 | 451 | 0 | 0 |
| z3-BooledASS-base n | 0 | 457 | 402.36 | 458.03 | 457 | 0 | 457 | 0 | 43 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 345 | 1548.92 | 1591.66 | 345 | 0 | 345 | 0 | 155 | 0 | 0 |