The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFDTLIRA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 1070
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | cvc5 | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 949 (base -1) | 743.47 | 860.31 | 949 | 173 | 776 | 121 | 0 | 119 | 0 |
| cvc5 | 0 | 936 | 492.58 | 607.89 | 936 | 156 | 780 | 134 | 0 | 43 | 0 |
| cvc5-cvc5-xyz ne | 0 | 936 (base +0) | 501.80 | 617.22 | 936 | 156 | 780 | 134 | 0 | 43 | 0 |
| SMTInterpol | 0 | 874 | 4257.41 | 2991.90 | 874 | 133 | 741 | 196 | 0 | 38 | 0 |
| z3-BooledASS-base n | 0 | 950 | 739.79 | 856.47 | 950 | 174 | 776 | 120 | 0 | 119 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 936 | 503.76 | 619.33 | 936 | 156 | 780 | 134 | 0 | 43 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 949 (base -1) | 743.47 | 860.31 | 949 | 173 | 776 | 121 | 0 | 119 | 0 |
| cvc5 | 0 | 936 | 492.58 | 607.89 | 936 | 156 | 780 | 134 | 0 | 43 | 0 |
| cvc5-cvc5-xyz ne | 0 | 936 (base +0) | 501.80 | 617.22 | 936 | 156 | 780 | 134 | 0 | 43 | 0 |
| SMTInterpol | 0 | 874 | 4257.41 | 2991.90 | 874 | 133 | 741 | 196 | 0 | 38 | 0 |
| z3-BooledASS-base n | 0 | 950 | 739.79 | 856.47 | 950 | 174 | 776 | 120 | 0 | 119 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 936 | 503.76 | 619.33 | 936 | 156 | 780 | 134 | 0 | 43 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 173 (base -1) | 603.12 | 624.45 | 173 | 173 | 0 | 1 | 896 | 0 | 0 |
| cvc5 | 0 | 156 | 349.58 | 368.31 | 156 | 156 | 0 | 18 | 896 | 5 | 0 |
| cvc5-cvc5-xyz ne | 0 | 156 (base +0) | 358.09 | 376.78 | 156 | 156 | 0 | 18 | 896 | 5 | 0 |
| SMTInterpol | 0 | 133 | 87.52 | 69.65 | 133 | 133 | 0 | 41 | 896 | 4 | 0 |
| z3-BooledASS-base n | 0 | 174 | 598.50 | 619.99 | 174 | 174 | 0 | 0 | 896 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 156 | 358.28 | 376.94 | 156 | 156 | 0 | 18 | 896 | 5 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 780 | 143.00 | 239.58 | 780 | 0 | 780 | 0 | 290 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 780 (base +0) | 143.71 | 240.44 | 780 | 0 | 780 | 0 | 290 | 0 | 0 |
| z3-BooledASS ne | 0 | 776 (base +0) | 140.35 | 235.86 | 776 | 0 | 776 | 4 | 290 | 3 | 0 |
| SMTInterpol | 0 | 741 | 4169.88 | 2922.25 | 741 | 0 | 741 | 39 | 290 | 25 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 780 | 145.48 | 242.39 | 780 | 0 | 780 | 0 | 290 | 0 | 0 |
| z3-BooledASS-base n | 0 | 776 | 141.28 | 236.48 | 776 | 0 | 776 | 4 | 290 | 3 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 945 (base -1) | 204.02 | 320.29 | 945 | 169 | 776 | 2 | 123 | 0 | 0 |
| cvc5 | 0 | 933 | 188.27 | 303.20 | 933 | 153 | 780 | 20 | 117 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 933 (base +0) | 191.87 | 306.91 | 933 | 153 | 780 | 21 | 116 | 0 | 0 |
| SMTInterpol | 0 | 859 | 1596.33 | 828.45 | 859 | 133 | 726 | 145 | 66 | 0 | 0 |
| z3-BooledASS-base n | 0 | 946 | 205.93 | 322.07 | 946 | 170 | 776 | 1 | 123 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 933 | 193.55 | 308.72 | 933 | 153 | 780 | 20 | 117 | 0 | 0 |