The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFDTLIA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 554
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | cvc5 | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 485 | 22657.40 | 22718.71 | 485 | 1 | 484 | 69 | 0 | 69 | 0 |
| cvc5-cvc5-xyz ne | 0 | 484 (base +0) | 20907.12 | 20968.57 | 484 | 1 | 483 | 70 | 0 | 70 | 0 |
| z3-BooledASS ne | 0 | 447 (base -5) | 1667.76 | 1722.79 | 447 | 0 | 447 | 107 | 0 | 94 | 0 |
| SMTInterpol | 0 | 120 | 6522.30 | 4769.43 | 121 | 0 | 121 | 433 | 0 | 353 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 484 | 21617.52 | 21679.14 | 484 | 1 | 483 | 70 | 0 | 70 | 0 |
| z3-BooledASS-base n | 0 | 452 | 2366.91 | 2422.44 | 452 | 0 | 452 | 102 | 0 | 86 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 485 | 22657.40 | 22718.71 | 485 | 1 | 484 | 69 | 0 | 69 | 0 |
| cvc5-cvc5-xyz ne | 0 | 484 (base +0) | 20907.12 | 20968.57 | 484 | 1 | 483 | 70 | 0 | 70 | 0 |
| z3-BooledASS ne | 0 | 447 (base -5) | 1667.76 | 1722.79 | 447 | 0 | 447 | 107 | 0 | 94 | 0 |
| SMTInterpol | 0 | 121 | 8070.26 | 5891.74 | 121 | 0 | 121 | 433 | 0 | 353 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 484 | 21617.52 | 21679.14 | 484 | 1 | 483 | 70 | 0 | 70 | 0 |
| z3-BooledASS-base n | 0 | 452 | 2366.91 | 2422.44 | 452 | 0 | 452 | 102 | 0 | 86 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz ne | 0 | 1 (base +0) | 596.20 | 596.37 | 1 | 1 | 0 | 0 | 553 | 0 | 0 |
| cvc5 | 0 | 1 | 604.38 | 604.55 | 1 | 1 | 0 | 0 | 553 | 0 | 0 |
| SMTInterpol | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 553 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 553 | 1 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 1 | 611.29 | 611.46 | 1 | 1 | 0 | 0 | 553 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 0 | 0 | 1 | 553 | 1 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 484 | 22053.03 | 22114.16 | 484 | 0 | 484 | 36 | 34 | 36 | 0 |
| cvc5-cvc5-xyz ne | 0 | 483 (base +0) | 20310.91 | 20372.20 | 483 | 0 | 483 | 37 | 34 | 37 | 0 |
| z3-BooledASS ne | 0 | 447 (base -5) | 1667.76 | 1722.79 | 447 | 0 | 447 | 73 | 34 | 65 | 0 |
| SMTInterpol | 0 | 121 | 8070.26 | 5891.74 | 121 | 0 | 121 | 399 | 34 | 320 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 483 | 21006.23 | 21067.68 | 483 | 0 | 483 | 37 | 34 | 37 | 0 |
| z3-BooledASS-base n | 0 | 452 | 2366.91 | 2422.44 | 452 | 0 | 452 | 68 | 34 | 57 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 440 (base -2) | 162.89 | 216.88 | 440 | 0 | 440 | 1 | 113 | 0 | 0 |
| cvc5 | 0 | 423 | 480.31 | 532.09 | 423 | 0 | 423 | 0 | 131 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 423 (base +0) | 484.82 | 536.83 | 423 | 0 | 423 | 0 | 131 | 0 | 0 |
| SMTInterpol | 0 | 106 | 621.20 | 243.28 | 106 | 0 | 106 | 0 | 448 | 0 | 0 |
| z3-BooledASS-base n | 0 | 442 | 179.35 | 233.40 | 442 | 0 | 442 | 1 | 111 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 423 | 483.75 | 535.87 | 423 | 0 | 423 | 0 | 131 | 0 | 0 |