The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFDT logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 713
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | cvc5 | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz ne | 0 | 253 (base +0) | 35759.65 | 35793.65 | 253 | 60 | 193 | 460 | 0 | 460 | 0 |
| cvc5 | 0 | 253 | 36827.44 | 36861.69 | 253 | 60 | 193 | 460 | 0 | 460 | 0 |
| z3-BooledASS ne | 0 | 107 (base +0) | 1179.62 | 1192.88 | 107 | 8 | 99 | 606 | 0 | 519 | 0 |
| SMTInterpol | 0 | 28 | 812.85 | 613.86 | 28 | 1 | 27 | 685 | 0 | 634 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 253 | 36823.97 | 36858.33 | 253 | 60 | 193 | 460 | 0 | 460 | 0 |
| z3-BooledASS-base n | 0 | 107 | 1333.37 | 1346.54 | 107 | 8 | 99 | 606 | 0 | 495 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz ne | 0 | 253 (base +0) | 35759.65 | 35793.65 | 253 | 60 | 193 | 460 | 0 | 460 | 0 |
| cvc5 | 0 | 253 | 36827.44 | 36861.69 | 253 | 60 | 193 | 460 | 0 | 460 | 0 |
| z3-BooledASS ne | 0 | 107 (base +0) | 1179.62 | 1192.88 | 107 | 8 | 99 | 606 | 0 | 519 | 0 |
| SMTInterpol | 0 | 28 | 812.85 | 613.86 | 28 | 1 | 27 | 685 | 0 | 634 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 253 | 36823.97 | 36858.33 | 253 | 60 | 193 | 460 | 0 | 460 | 0 |
| z3-BooledASS-base n | 0 | 107 | 1333.37 | 1346.54 | 107 | 8 | 99 | 606 | 0 | 495 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz ne | 0 | 60 (base +0) | 28802.20 | 28812.10 | 60 | 60 | 0 | 1 | 652 | 1 | 0 |
| cvc5 | 0 | 60 | 28807.78 | 28817.55 | 60 | 60 | 0 | 1 | 652 | 1 | 0 |
| z3-BooledASS ne | 0 | 8 (base +0) | 1.79 | 2.81 | 8 | 8 | 0 | 53 | 652 | 35 | 0 |
| SMTInterpol | 0 | 1 | 0.88 | 0.59 | 1 | 1 | 0 | 60 | 652 | 42 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 60 | 28803.91 | 28813.83 | 60 | 60 | 0 | 1 | 652 | 1 | 0 |
| z3-BooledASS-base n | 0 | 8 | 1.63 | 2.63 | 8 | 8 | 0 | 53 | 652 | 35 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz ne | 0 | 193 (base +0) | 6957.45 | 6981.55 | 193 | 0 | 193 | 6 | 514 | 6 | 0 |
| cvc5 | 0 | 193 | 8019.65 | 8044.15 | 193 | 0 | 193 | 6 | 514 | 6 | 0 |
| z3-BooledASS ne | 0 | 99 (base +0) | 1177.83 | 1190.07 | 99 | 0 | 99 | 100 | 514 | 91 | 0 |
| SMTInterpol | 0 | 27 | 811.98 | 613.28 | 27 | 0 | 27 | 172 | 514 | 168 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 193 | 8020.06 | 8044.50 | 193 | 0 | 193 | 6 | 514 | 6 | 0 |
| z3-BooledASS-base n | 0 | 99 | 1331.74 | 1343.91 | 99 | 0 | 99 | 100 | 514 | 85 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz ne | 0 | 151 (base +3) | 145.43 | 163.91 | 151 | 1 | 150 | 0 | 562 | 0 | 0 |
| cvc5 | 0 | 148 | 122.42 | 140.65 | 148 | 1 | 147 | 0 | 565 | 0 | 0 |
| z3-BooledASS ne | 0 | 104 (base +0) | 38.11 | 50.85 | 104 | 8 | 96 | 6 | 603 | 0 | 0 |
| SMTInterpol | 0 | 23 | 182.51 | 81.80 | 23 | 1 | 22 | 27 | 663 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 148 | 124.13 | 142.28 | 148 | 1 | 147 | 0 | 565 | 0 | 0 |
| z3-BooledASS-base n | 0 | 104 | 38.15 | 50.84 | 104 | 8 | 96 | 5 | 604 | 0 | 0 |