The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFBVDTNIRA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 525
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 423 | 248.27 | 300.81 | 423 | 0 | 423 | 102 | 0 | 6 | 0 |
| cvc5-cvc5-xyz ne | 0 | 418 (base -5) | 2437.38 | 2489.50 | 418 | 0 | 418 | 107 | 0 | 107 | 0 |
| SMTInterpol | 0 | 343 | 10067.26 | 8513.43 | 343 | 0 | 343 | 182 | 0 | 129 | 0 |
| z3-BooledASS ne | 0 | 0 (base -411) | 0.00 | 0.00 | 0 | 0 | 0 | 525 | 0 | 203 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 423 | 251.43 | 304.17 | 423 | 0 | 423 | 102 | 0 | 6 | 0 |
| z3-BooledASS-base n | 0 | 411 | 93.38 | 144.04 | 411 | 0 | 411 | 114 | 0 | 114 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 423 | 248.27 | 300.81 | 423 | 0 | 423 | 102 | 0 | 6 | 0 |
| cvc5-cvc5-xyz ne | 0 | 418 (base -5) | 2437.38 | 2489.50 | 418 | 0 | 418 | 107 | 0 | 107 | 0 |
| SMTInterpol | 0 | 343 | 10067.26 | 8513.43 | 343 | 0 | 343 | 182 | 0 | 129 | 0 |
| z3-BooledASS ne | 0 | 0 (base -411) | 0.00 | 0.00 | 0 | 0 | 0 | 525 | 0 | 203 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 423 | 251.43 | 304.17 | 423 | 0 | 423 | 102 | 0 | 6 | 0 |
| z3-BooledASS-base n | 0 | 411 | 93.38 | 144.04 | 411 | 0 | 411 | 114 | 0 | 114 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 423 | 248.27 | 300.81 | 423 | 0 | 423 | 1 | 101 | 1 | 0 |
| cvc5-cvc5-xyz ne | 0 | 418 (base -5) | 2437.38 | 2489.50 | 418 | 0 | 418 | 6 | 101 | 6 | 0 |
| SMTInterpol | 0 | 343 | 10067.26 | 8513.43 | 343 | 0 | 343 | 81 | 101 | 67 | 0 |
| z3-BooledASS ne | 0 | 0 (base -411) | 0.00 | 0.00 | 0 | 0 | 0 | 424 | 101 | 102 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 423 | 251.43 | 304.17 | 423 | 0 | 423 | 1 | 101 | 1 | 0 |
| z3-BooledASS-base n | 0 | 411 | 93.38 | 144.04 | 411 | 0 | 411 | 13 | 101 | 13 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 422 | 100.44 | 152.84 | 422 | 0 | 422 | 95 | 8 | 0 | 0 |
| cvc5-cvc5-xyz | 0 | 415 (base -7) | 95.42 | 146.96 | 415 | 0 | 415 | 16 | 94 | 16 | 0 |
| SMTInterpol | 0 | 324 | 1164.77 | 447.71 | 324 | 0 | 324 | 4 | 197 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base -411) | 0.00 | 0.00 | 0 | 0 | 0 | 322 | 203 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 422 | 103.42 | 156.02 | 422 | 0 | 422 | 95 | 8 | 0 | 0 |
| z3-BooledASS-base n | 0 | 411 | 93.38 | 144.04 | 411 | 0 | 411 | 0 | 114 | 0 | 0 |