The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UFBVDTLIA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 24
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 24 (base +0) | 4.09 | 7.01 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 24 | 4.12 | 7.11 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 24 (base +0) | 4.32 | 7.33 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 23 | 94.25 | 35.65 | 23 | 0 | 23 | 1 | 0 | 1 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 24 | 4.11 | 7.08 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 24 | 4.15 | 7.08 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 24 (base +0) | 4.09 | 7.01 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 24 | 4.12 | 7.11 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 24 (base +0) | 4.32 | 7.33 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 23 | 94.25 | 35.65 | 23 | 0 | 23 | 1 | 0 | 1 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 24 | 4.11 | 7.08 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 24 | 4.15 | 7.08 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 24 (base +0) | 4.09 | 7.01 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 24 | 4.12 | 7.11 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 24 (base +0) | 4.32 | 7.33 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 23 | 94.25 | 35.65 | 23 | 0 | 23 | 1 | 0 | 1 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 24 | 4.11 | 7.08 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 24 | 4.15 | 7.08 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 24 (base +0) | 4.09 | 7.01 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 24 | 4.12 | 7.11 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 24 (base +0) | 4.32 | 7.33 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 23 | 94.25 | 35.65 | 23 | 0 | 23 | 0 | 1 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 24 | 4.11 | 7.08 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 24 | 4.15 | 7.08 | 24 | 0 | 24 | 0 | 0 | 0 | 0 |