The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the UF logic in the Incremental Track. Chart
Results were generated on 2026-07-25
Benchmarks: 806
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 8671 | 304298.67 | 304309.94 | 0 | 806 | 0 | 379 | 0 |
| SMTInterpol | 0 | 4555 | 749445.32 | 546979.46 | 0 | 806 | 0 | 470 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 4.85 | 6.19 | 0 | 806 | 0 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 3023.13 | 1121.05 | 0 | 806 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 806 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 6305 | 1046.66 | 1046.66 | 0 | 484 | 322 | 117 | 0 |
| SMTInterpol | 0 | 2411 | 348.16 | 348.16 | 0 | 152 | 654 | 32 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 4.85 | 6.19 | 0 | 806 | 0 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 3023.13 | 1121.05 | 0 | 806 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 806 | 0 | 0 | 0 |