The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFLRA logic in the Incremental Track. Chart
Results were generated on 2026-07-25
Benchmarks: 705
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| cvc5 | - | - | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 3845 | 10102.05 | 10101.52 | 0 | 705 | 0 | 2 | 0 |
| Yices2 | 0 | 3840 | 3691.56 | 3691.56 | 0 | 705 | 0 | 2 | 0 |
| OpenSMT | 0 | 3827 | 14092.73 | 14091.13 | 0 | 705 | 0 | 13 | 0 |
| SMTInterpol | 0 | 3787 | 11101.56 | 11101.56 | 0 | 705 | 0 | 10 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 4.22 | 5.41 | 0 | 705 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 705 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 3614 | 550.93 | 550.93 | 0 | 690 | 15 | 0 | 0 |
| OpenSMT | 0 | 3292 | 567.40 | 567.40 | 0 | 650 | 55 | 4 | 0 |
| cvc5 | 0 | 3221 | 996.87 | 996.87 | 0 | 655 | 50 | 0 | 0 |
| SMTInterpol | 0 | 3113 | 1355.84 | 1355.84 | 0 | 642 | 63 | 1 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 4.22 | 5.41 | 0 | 705 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 705 | 0 | 0 | 0 |