The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFLIA logic in the Unsat Core Track. Chart
Results were generated on 2026-07-25
Benchmarks: 24
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| Yices2 | Yices2 | - | Yices2 | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 307375 (base +0) | 1876.19 | 1879.18 | 23 | 23 | 1 | 0 | 1 | 0 |
| Yices2 | 0 | 307200 | 1562.82 | 1565.86 | 23 | 23 | 1 | 0 | 1 | 0 |
| SMTInterpol | 0 | 31774 | 1299.98 | 1162.42 | 23 | 23 | 1 | 0 | 1 | 0 |
| OpenSMT | 0 | 10398 | 1246.84 | 1249.45 | 20 | 20 | 4 | 0 | 4 | 0 |
| cvc5 | 0 | 9575 | 37.20 | 39.54 | 19 | 19 | 5 | 0 | 5 | 0 |
| OpenSMT (min-ucore) | 0 | 9359 | 1060.71 | 1063.21 | 19 | 19 | 5 | 0 | 5 | 0 |
| z3-BooledASS-base n | 0 | 307375 | 1814.76 | 1817.75 | 23 | 23 | 1 | 0 | 1 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 307375 (base +0) | 1876.19 | 1879.18 | 23 | 23 | 1 | 0 | 1 | 0 |
| Yices2 | 0 | 307200 | 1562.82 | 1565.86 | 23 | 23 | 1 | 0 | 1 | 0 |
| SMTInterpol | 0 | 31774 | 1299.98 | 1162.42 | 23 | 23 | 1 | 0 | 1 | 0 |
| OpenSMT | 0 | 10398 | 1246.84 | 1249.45 | 20 | 20 | 4 | 0 | 4 | 0 |
| cvc5 | 0 | 9575 | 37.20 | 39.54 | 19 | 19 | 5 | 0 | 5 | 0 |
| OpenSMT (min-ucore) | 0 | 9359 | 1060.71 | 1063.21 | 19 | 19 | 5 | 0 | 5 | 0 |
| z3-BooledASS-base n | 0 | 307375 | 1814.76 | 1817.75 | 23 | 23 | 1 | 0 | 1 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 307375 (base +0) | 1876.19 | 1879.18 | 23 | 23 | 1 | 0 | 1 | 0 |
| Yices2 | 0 | 307200 | 1562.82 | 1565.86 | 23 | 23 | 1 | 0 | 1 | 0 |
| SMTInterpol | 0 | 31774 | 1299.98 | 1162.42 | 23 | 23 | 1 | 0 | 1 | 0 |
| OpenSMT | 0 | 10398 | 1246.84 | 1249.45 | 20 | 20 | 4 | 0 | 4 | 0 |
| cvc5 | 0 | 9575 | 37.20 | 39.54 | 19 | 19 | 5 | 0 | 5 | 0 |
| OpenSMT (min-ucore) | 0 | 9359 | 1060.71 | 1063.21 | 19 | 19 | 5 | 0 | 5 | 0 |
| z3-BooledASS-base n | 0 | 307375 | 1814.76 | 1817.75 | 23 | 23 | 1 | 0 | 1 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 285946 | 9.73 | 12.26 | 20 | 20 | 0 | 4 | 0 | 0 |
| z3-BooledASS ne | 0 | 11767 (base +0) | 24.53 | 26.90 | 19 | 19 | 0 | 5 | 0 | 0 |
| SMTInterpol | 0 | 10471 | 61.60 | 28.09 | 20 | 20 | 0 | 4 | 0 | 0 |
| cvc5 | 0 | 8810 | 7.60 | 9.80 | 18 | 18 | 0 | 6 | 0 | 0 |
| OpenSMT | 0 | 1064 | 5.09 | 7.31 | 18 | 18 | 0 | 6 | 0 | 0 |
| OpenSMT (min-ucore) | 0 | 587 | 5.12 | 7.23 | 17 | 17 | 0 | 7 | 0 | 0 |
| z3-BooledASS-base n | 0 | 11767 | 24.15 | 26.51 | 19 | 19 | 0 | 5 | 0 | 0 |