The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFDTLIA logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 76
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5-cvc5-xyz | cvc5-cvc5-xyz | cvc5-cvc5-xyz | SMTInterpol | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz | 0 | 62 (base +23) | 4492.82 | 4500.75 | 62 | 54 | 8 | 14 | 0 | 14 | 0 |
| SMTInterpol | 0 | 58 | 10330.18 | 9212.03 | 58 | 45 | 13 | 18 | 0 | 18 | 0 |
| z3-BooledASS ne | 0 | 55 (base +0) | 662.97 | 669.78 | 55 | 43 | 12 | 21 | 0 | 21 | 0 |
| cvc5 | 0 | 40 | 6357.90 | 6363.55 | 40 | 32 | 8 | 36 | 0 | 36 | 0 |
| z3-BooledASS-base n | 0 | 55 | 662.43 | 669.42 | 55 | 43 | 12 | 21 | 0 | 21 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 39 | 6002.25 | 6007.76 | 39 | 31 | 8 | 37 | 0 | 37 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz | 0 | 62 (base +23) | 4492.82 | 4500.75 | 62 | 54 | 8 | 14 | 0 | 14 | 0 |
| SMTInterpol | 0 | 58 | 10330.18 | 9212.03 | 58 | 45 | 13 | 18 | 0 | 18 | 0 |
| z3-BooledASS ne | 0 | 55 (base +0) | 662.97 | 669.78 | 55 | 43 | 12 | 21 | 0 | 21 | 0 |
| cvc5 | 0 | 40 | 6357.90 | 6363.55 | 40 | 32 | 8 | 36 | 0 | 36 | 0 |
| z3-BooledASS-base n | 0 | 55 | 662.43 | 669.42 | 55 | 43 | 12 | 21 | 0 | 21 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 39 | 6002.25 | 6007.76 | 39 | 31 | 8 | 37 | 0 | 37 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| cvc5-cvc5-xyz | 0 | 54 (base +23) | 4446.27 | 4453.23 | 54 | 54 | 0 | 1 | 21 | 1 | 0 |
| SMTInterpol | 0 | 45 | 8057.70 | 7204.37 | 45 | 45 | 0 | 10 | 21 | 10 | 0 |
| z3-BooledASS ne | 0 | 43 (base +0) | 490.79 | 496.10 | 43 | 43 | 0 | 12 | 21 | 12 | 0 |
| cvc5 | 0 | 32 | 5728.86 | 5733.49 | 32 | 32 | 0 | 23 | 21 | 23 | 0 |
| z3-BooledASS-base n | 0 | 43 | 491.17 | 496.63 | 43 | 43 | 0 | 12 | 21 | 12 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 31 | 5359.01 | 5363.42 | 31 | 31 | 0 | 24 | 21 | 24 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| SMTInterpol | 0 | 13 | 2272.47 | 2007.66 | 13 | 0 | 13 | 0 | 63 | 0 | 0 |
| z3-BooledASS ne | 0 | 12 (base +0) | 172.18 | 173.68 | 12 | 0 | 12 | 1 | 63 | 1 | 0 |
| cvc5-cvc5-xyz ne | 0 | 8 (base +0) | 46.55 | 47.52 | 8 | 0 | 8 | 5 | 63 | 5 | 0 |
| cvc5 | 0 | 8 | 629.05 | 630.06 | 8 | 0 | 8 | 5 | 63 | 5 | 0 |
| z3-BooledASS-base n | 0 | 12 | 171.26 | 172.79 | 12 | 0 | 12 | 1 | 63 | 1 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 8 | 643.24 | 644.34 | 8 | 0 | 8 | 5 | 63 | 5 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 50 (base +0) | 243.40 | 249.53 | 50 | 42 | 8 | 0 | 26 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 43 (base +20) | 278.08 | 283.36 | 43 | 35 | 8 | 0 | 33 | 0 | 0 |
| cvc5 | 0 | 24 | 200.80 | 203.74 | 24 | 18 | 6 | 0 | 52 | 0 | 0 |
| SMTInterpol | 0 | 21 | 364.68 | 169.55 | 21 | 16 | 5 | 0 | 55 | 0 | 0 |
| z3-BooledASS-base n | 0 | 50 | 244.73 | 251.03 | 50 | 42 | 8 | 0 | 26 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 23 | 205.48 | 208.38 | 23 | 17 | 6 | 0 | 53 | 0 | 0 |