QF_UFDTLIA (Model Validation Track)

Competition results for the QF_UFDTLIA logic in the Model Validation Track. Chart

Results were generated on 2026-07-25

Benchmarks: 45
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential Performance	Parallel Performance	SAT Performance (parallel)	UNSAT Performance (parallel)	24 seconds Performance (parallel)
cvc5	cvc5	cvc5	-	cvc5

Sequential Performance Performance

Solver	Correct Score	CPU Time Score	Wall Time Score	Solved	Solved SAT	Unsolved	Timeout
z3-BooledASS ^ne	43 (base +0)	489.77	495.20	43	43	2	2
cvc5	32	5719.03	5723.55	32	32	13	13
SMTInterpol	16	1870.90	1562.44	16	16	29	1
z3-BooledASS-base ⁿ	43	491.76	497.10	43	43	2	2

(base +/- n): for derived solvers: increment over base solver
^ne: not eligible for winning as it does not substantially improve over the base solver (at least 10 % improvement in PAR2 score) ⁿ: non-competing solver

Parallel Performance Performance

Solver	Correct Score	CPU Time Score	Wall Time Score	Solved	Solved SAT	Unsolved	Timeout
z3-BooledASS ^ne	43 (base +0)	489.77	495.20	43	43	2	2
cvc5	32	5719.03	5723.55	32	32	13	13
SMTInterpol	16	1870.90	1562.44	16	16	29	1
z3-BooledASS-base ⁿ	43	491.76	497.10	43	43	2	2

SAT Performance Performance

Solver	Correct Score	CPU Time Score	Wall Time Score	Solved	Solved SAT	Unsolved	Timeout
z3-BooledASS ^ne	43 (base +0)	489.77	495.20	43	43	2	2
cvc5	32	5719.03	5723.55	32	32	13	13
SMTInterpol	16	1870.90	1562.44	16	16	29	1
z3-BooledASS-base ⁿ	43	491.76	497.10	43	43	2	2

24 seconds Performance Performance

Solver	Correct Score	CPU Time Score	Wall Time Score	Solved	Solved SAT	Unsolved	Abstained
z3-BooledASS ^ne	42 (base +0)	201.61	206.87	42	42	0	3
cvc5	18	172.01	174.28	18	18	0	27
SMTInterpol	6	118.63	55.71	6	6	10	29
z3-BooledASS-base ⁿ	42	200.42	205.63	42	42	0	3

SMT-COMP 2026