The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_UFBVLIA logic in the Incremental Track. Chart
Results were generated on 2026-07-25
Benchmarks: 179
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| Yices2 | - | - | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 207 | 11.11 | 11.11 | 0 | 179 | 0 | 0 | 0 |
| cvc5 | 0 | 207 | 30.82 | 30.82 | 0 | 179 | 0 | 0 | 0 |
| SMTInterpol | 0 | 207 | 196.13 | 196.13 | 0 | 179 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 1.11 | 1.41 | 0 | 179 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 179 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 207 | 11.11 | 11.11 | 0 | 179 | 0 | 0 | 0 |
| cvc5 | 0 | 207 | 30.82 | 30.82 | 0 | 179 | 0 | 0 | 0 |
| SMTInterpol | 0 | 206 | 171.12 | 171.12 | 0 | 178 | 1 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 1.11 | 1.41 | 0 | 179 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 179 | 0 | 0 | 0 |