The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_LIA logic in the Incremental Track. Chart
Results were generated on 2026-07-25
Benchmarks: 69
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| Yices2 | - | - | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 14783788 | 26304.09 | 26304.09 | 0 | 69 | 0 | 15 | 0 |
| SMTInterpol | 0 | 14494985 | 43907.26 | 43907.26 | 0 | 69 | 0 | 35 | 0 |
| cvc5 | 0 | 3861374 | 61089.95 | 61089.95 | 0 | 69 | 0 | 54 | 0 |
| OpenSMT | 0 | 1150789 | 52463.19 | 52463.19 | 0 | 69 | 0 | 43 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 0.41 | 0.52 | 0 | 69 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 69 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 874094 | 104.35 | 104.35 | 0 | 18 | 51 | 0 | 0 |
| OpenSMT | 0 | 1717 | 84.53 | 84.53 | 0 | 13 | 56 | 0 | 0 |
| cvc5 | 0 | 1111 | 63.80 | 63.80 | 0 | 9 | 60 | 0 | 0 |
| SMTInterpol | 0 | 606 | 35.75 | 35.75 | 0 | 4 | 65 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 0.41 | 0.52 | 0 | 69 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 69 | 0 | 0 | 0 |