The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_IDL logic in the Model Validation Track. Chart
Results were generated on 2026-07-25
Benchmarks: 548
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| Yices2 | Yices2 | Yices2 | - | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 494 (base -1) | 24209.35 | 24271.75 | 494 | 494 | 54 | 0 | 51 | 0 |
| Yices2 | 0 | 483 | 11930.41 | 11991.30 | 483 | 483 | 65 | 0 | 62 | 0 |
| OpenSMT | 0 | 444 | 28861.39 | 28919.12 | 444 | 444 | 104 | 0 | 103 | 0 |
| cvc5 | 0 | 425 | 37999.61 | 38056.03 | 425 | 425 | 123 | 0 | 122 | 0 |
| SMTInterpol | 0 | 328 | 23210.51 | 19807.48 | 328 | 328 | 220 | 0 | 219 | 0 |
| z3-BooledASS-base n | 0 | 495 | 22826.37 | 22888.67 | 495 | 495 | 53 | 0 | 52 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 494 (base -1) | 24209.35 | 24271.75 | 494 | 494 | 54 | 0 | 51 | 0 |
| Yices2 | 0 | 483 | 11930.41 | 11991.30 | 483 | 483 | 65 | 0 | 62 | 0 |
| OpenSMT | 0 | 444 | 28861.39 | 28919.12 | 444 | 444 | 104 | 0 | 103 | 0 |
| cvc5 | 0 | 425 | 37999.61 | 38056.03 | 425 | 425 | 123 | 0 | 122 | 0 |
| SMTInterpol | 0 | 328 | 23210.51 | 19807.48 | 328 | 328 | 220 | 0 | 219 | 0 |
| z3-BooledASS-base n | 0 | 495 | 22826.37 | 22888.67 | 495 | 495 | 53 | 0 | 52 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| z3-BooledASS ne | 0 | 494 (base -1) | 24209.35 | 24271.75 | 494 | 494 | 54 | 0 | 51 | 0 |
| Yices2 | 0 | 483 | 11930.41 | 11991.30 | 483 | 483 | 65 | 0 | 62 | 0 |
| OpenSMT | 0 | 444 | 28861.39 | 28919.12 | 444 | 444 | 104 | 0 | 103 | 0 |
| cvc5 | 0 | 425 | 37999.61 | 38056.03 | 425 | 425 | 123 | 0 | 122 | 0 |
| SMTInterpol | 0 | 328 | 23210.51 | 19807.48 | 328 | 328 | 220 | 0 | 219 | 0 |
| z3-BooledASS-base n | 0 | 495 | 22826.37 | 22888.67 | 495 | 495 | 53 | 0 | 52 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 435 | 704.81 | 758.90 | 435 | 435 | 2 | 111 | 0 | 0 |
| z3-BooledASS ne | 0 | 404 (base -1) | 1007.26 | 1056.97 | 404 | 404 | 2 | 142 | 0 | 0 |
| OpenSMT | 0 | 296 | 1183.33 | 1220.10 | 296 | 296 | 0 | 252 | 0 | 0 |
| cvc5 | 0 | 273 | 1062.08 | 1095.69 | 273 | 273 | 0 | 275 | 0 | 0 |
| SMTInterpol | 0 | 234 | 2731.55 | 1309.18 | 234 | 234 | 0 | 314 | 0 | 0 |
| z3-BooledASS-base n | 0 | 405 | 995.86 | 1045.70 | 405 | 405 | 1 | 142 | 0 | 0 |