The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_Equality division in the Model Validation Track. Chart
Results were generated on 2026-07-25
Benchmarks: 714
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| Yices2 | Yices2 | Yices2 | - | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 714 | 129.49 | 219.23 | 714 | 714 | 0 | 0 | 0 | 0 |
| OpenSMT | 0 | 714 | 185.81 | 274.19 | 714 | 714 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 714 | 232.73 | 320.22 | 714 | 714 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 714 | 1614.58 | 726.45 | 714 | 714 | 0 | 0 | 0 | 0 |
| plat-smt | 0 | 703 | 139.61 | 227.34 | 703 | 703 | 11 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 2 (base +0) | 0.32 | 0.56 | 2 | 2 | 712 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 2 | 0.34 | 0.59 | 2 | 2 | 712 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 714 | 129.49 | 219.23 | 714 | 714 | 0 | 0 | 0 | 0 |
| OpenSMT | 0 | 714 | 185.81 | 274.19 | 714 | 714 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 714 | 232.73 | 320.22 | 714 | 714 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 714 | 1614.58 | 726.45 | 714 | 714 | 0 | 0 | 0 | 0 |
| plat-smt | 0 | 703 | 139.61 | 227.34 | 703 | 703 | 11 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 2 (base +0) | 0.32 | 0.56 | 2 | 2 | 712 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 2 | 0.34 | 0.59 | 2 | 2 | 712 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 714 | 129.49 | 219.23 | 714 | 714 | 0 | 0 | 0 | 0 |
| OpenSMT | 0 | 714 | 185.81 | 274.19 | 714 | 714 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 714 | 232.73 | 320.22 | 714 | 714 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 714 | 1614.58 | 726.45 | 714 | 714 | 0 | 0 | 0 | 0 |
| plat-smt | 0 | 703 | 139.61 | 227.34 | 703 | 703 | 11 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 2 (base +0) | 0.32 | 0.56 | 2 | 2 | 712 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 2 | 0.34 | 0.59 | 2 | 2 | 712 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 714 | 129.49 | 219.23 | 714 | 714 | 0 | 0 | 0 | 0 |
| OpenSMT | 0 | 714 | 185.81 | 274.19 | 714 | 714 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 714 | 232.73 | 320.22 | 714 | 714 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 714 | 1614.58 | 726.45 | 714 | 714 | 0 | 0 | 0 | 0 |
| plat-smt | 0 | 703 | 139.61 | 227.34 | 703 | 703 | 11 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 2 (base +0) | 0.32 | 0.56 | 2 | 2 | 712 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 2 | 0.34 | 0.59 | 2 | 2 | 712 | 0 | 0 | 0 |