The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_BVLRA logic in the Incremental Track. Chart
Results were generated on 2026-07-25
Benchmarks: 504
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| Yices2 | - | - | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 16158 | 385.31 | 385.31 | 0 | 504 | 0 | 1 | 0 |
| SMTInterpol | 0 | 16147 | 3979.54 | 3979.54 | 0 | 504 | 0 | 2 | 0 |
| cvc5 | 0 | 16110 | 3901.41 | 3901.41 | 0 | 504 | 0 | 8 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 3.05 | 3.88 | 0 | 504 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 504 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 15948 | 248.19 | 248.19 | 0 | 501 | 3 | 1 | 0 |
| cvc5 | 0 | 14698 | 735.34 | 735.34 | 0 | 488 | 16 | 6 | 0 |
| SMTInterpol | 0 | 12162 | 1884.05 | 1884.05 | 0 | 458 | 46 | 1 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 3.05 | 3.88 | 0 | 504 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 504 | 0 | 0 | 0 |