The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_AX logic in the Unsat Core Track. Chart
Results were generated on 2026-07-25
Benchmarks: 202
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| Yices2 | Yices2 | - | Yices2 | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 38641 | 32.83 | 57.79 | 202 | 202 | 0 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 38181 (base +0) | 45.46 | 70.27 | 202 | 202 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 32502 | 111.90 | 136.59 | 202 | 202 | 0 | 0 | 0 | 0 |
| OpenSMT (min-ucore) | 0 | 627 | 7200.47 | 7212.00 | 89 | 89 | 113 | 0 | 113 | 0 |
| OpenSMT | 0 | 430 | 114.04 | 139.18 | 202 | 202 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 429 | 611.32 | 273.99 | 202 | 202 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 38181 | 45.63 | 70.39 | 202 | 202 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 38641 | 32.83 | 57.79 | 202 | 202 | 0 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 38181 (base +0) | 45.46 | 70.27 | 202 | 202 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 32502 | 111.90 | 136.59 | 202 | 202 | 0 | 0 | 0 | 0 |
| OpenSMT (min-ucore) | 0 | 627 | 7200.47 | 7212.00 | 89 | 89 | 113 | 0 | 113 | 0 |
| OpenSMT | 0 | 430 | 114.04 | 139.18 | 202 | 202 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 429 | 611.32 | 273.99 | 202 | 202 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 38181 | 45.63 | 70.39 | 202 | 202 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 38641 | 32.83 | 57.79 | 202 | 202 | 0 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 38181 (base +0) | 45.46 | 70.27 | 202 | 202 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 32502 | 111.90 | 136.59 | 202 | 202 | 0 | 0 | 0 | 0 |
| OpenSMT (min-ucore) | 0 | 627 | 7200.47 | 7212.00 | 89 | 89 | 113 | 0 | 113 | 0 |
| OpenSMT | 0 | 430 | 114.04 | 139.18 | 202 | 202 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 429 | 611.32 | 273.99 | 202 | 202 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 38181 | 45.63 | 70.39 | 202 | 202 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 38641 | 32.83 | 57.79 | 202 | 202 | 0 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 38181 (base +0) | 45.46 | 70.27 | 202 | 202 | 0 | 0 | 0 | 0 |
| cvc5 | 0 | 32502 | 111.90 | 136.59 | 202 | 202 | 0 | 0 | 0 | 0 |
| OpenSMT (min-ucore) | 0 | 552 | 145.33 | 153.53 | 66 | 66 | 0 | 136 | 0 | 0 |
| OpenSMT | 0 | 430 | 114.04 | 139.18 | 202 | 202 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 429 | 611.32 | 273.99 | 202 | 202 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 38181 | 45.63 | 70.39 | 202 | 202 | 0 | 0 | 0 | 0 |