QF_AUFNIA (Model Validation Track)

Competition results for the QF_AUFNIA logic in the Model Validation Track. Chart

Results were generated on 2026-07-25

Benchmarks: 5
Time Limit: 1200 seconds
Memory Limit: 30720 GB

Winners

Sequential Performance	Parallel Performance	SAT Performance (parallel)	UNSAT Performance (parallel)	24 seconds Performance (parallel)
SMTInterpol	SMTInterpol	SMTInterpol	-	SMTInterpol

Sequential Performance Performance

Solver	Error Score	Correct Score	CPU Time Score	Wall Time Score	Solved	Solved SAT	Unsolved	Timeout
SMTInterpol	0	5	14.35	5.65	5	5	0	0
cvc5	0	5	12.24	12.86	5	5	0	0
z3-BooledASS ^ne	0	0 (base +0)	0.00	0.00	0	0	5	1
Yices2	5	0	0.00	0.00	0	0	5	0
z3-BooledASS-base ⁿ	0	0	0.00	0.00	0	0	5	1

(base +/- n): for derived solvers: increment over base solver
^ne: not eligible for winning as it does not substantially improve over the base solver (at least 10 % improvement in PAR2 score) ⁿ: non-competing solver

Parallel Performance Performance

Solver	Error Score	Correct Score	CPU Time Score	Wall Time Score	Solved	Solved SAT	Unsolved	Timeout
SMTInterpol	0	5	14.35	5.65	5	5	0	0
cvc5	0	5	12.24	12.86	5	5	0	0
z3-BooledASS ^ne	0	0 (base +0)	0.00	0.00	0	0	5	1
Yices2	5	0	0.00	0.00	0	0	5	0
z3-BooledASS-base ⁿ	0	0	0.00	0.00	0	0	5	1

SAT Performance Performance

Solver	Error Score	Correct Score	CPU Time Score	Wall Time Score	Solved	Solved SAT	Unsolved	Timeout
SMTInterpol	0	5	14.35	5.65	5	5	0	0
cvc5	0	5	12.24	12.86	5	5	0	0
z3-BooledASS ^ne	0	0 (base +0)	0.00	0.00	0	0	5	1
Yices2	5	0	0.00	0.00	0	0	5	0
z3-BooledASS-base ⁿ	0	0	0.00	0.00	0	0	5	1

24 seconds Performance Performance

Solver	Error Score	Correct Score	CPU Time Score	Wall Time Score	Solved	Solved SAT	Unsolved	Abstained
SMTInterpol	0	5	14.35	5.65	5	5	0	0
cvc5	0	5	12.24	12.86	5	5	0	0
z3-BooledASS ^ne	0	0 (base +0)	0.00	0.00	0	0	4	1
Yices2	5	0	0.00	0.00	0	0	5	0
z3-BooledASS-base ⁿ	0	0	0.00	0.00	0	0	4	1

SMT-COMP 2026