The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_AUFLIA logic in the Unsat Core Track. Chart
Results were generated on 2026-07-25
Benchmarks: 300
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| cvc5 | cvc5 | - | cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 24092 | 118.09 | 155.33 | 300 | 300 | 0 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 23010 (base +0) | 60.33 | 97.15 | 300 | 300 | 0 | 0 | 0 | 0 |
| Yices2 | 0 | 16180 | 53.36 | 90.60 | 300 | 300 | 0 | 0 | 0 | 0 |
| OpenSMT (min-ucore) | 0 | 3439 | 9465.82 | 9499.62 | 265 | 265 | 35 | 0 | 35 | 0 |
| OpenSMT | 0 | 2741 | 123.07 | 160.89 | 300 | 300 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 1309 | 1184.63 | 585.10 | 300 | 300 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 23010 | 60.27 | 97.11 | 300 | 300 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 24092 | 118.09 | 155.33 | 300 | 300 | 0 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 23010 (base +0) | 60.33 | 97.15 | 300 | 300 | 0 | 0 | 0 | 0 |
| Yices2 | 0 | 16180 | 53.36 | 90.60 | 300 | 300 | 0 | 0 | 0 | 0 |
| OpenSMT (min-ucore) | 0 | 3439 | 9465.82 | 9499.62 | 265 | 265 | 35 | 0 | 35 | 0 |
| OpenSMT | 0 | 2741 | 123.07 | 160.89 | 300 | 300 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 1309 | 1184.63 | 585.10 | 300 | 300 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 23010 | 60.27 | 97.11 | 300 | 300 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 24092 | 118.09 | 155.33 | 300 | 300 | 0 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 23010 (base +0) | 60.33 | 97.15 | 300 | 300 | 0 | 0 | 0 | 0 |
| Yices2 | 0 | 16180 | 53.36 | 90.60 | 300 | 300 | 0 | 0 | 0 | 0 |
| OpenSMT (min-ucore) | 0 | 3439 | 9465.82 | 9499.62 | 265 | 265 | 35 | 0 | 35 | 0 |
| OpenSMT | 0 | 2741 | 123.07 | 160.89 | 300 | 300 | 0 | 0 | 0 | 0 |
| SMTInterpol | 0 | 1309 | 1184.63 | 585.10 | 300 | 300 | 0 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 23010 | 60.27 | 97.11 | 300 | 300 | 0 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 24092 | 118.09 | 155.33 | 300 | 300 | 0 | 0 | 0 | 0 |
| z3-BooledASS ne | 0 | 23010 (base +0) | 60.33 | 97.15 | 300 | 300 | 0 | 0 | 0 | 0 |
| Yices2 | 0 | 16180 | 53.36 | 90.60 | 300 | 300 | 0 | 0 | 0 | 0 |
| OpenSMT | 0 | 2741 | 123.07 | 160.89 | 300 | 300 | 0 | 0 | 0 | 0 |
| OpenSMT (min-ucore) | 0 | 1523 | 345.67 | 373.47 | 224 | 224 | 0 | 76 | 0 | 0 |
| SMTInterpol | 0 | 1303 | 614.29 | 320.99 | 297 | 297 | 0 | 3 | 0 | 0 |
| z3-BooledASS-base n | 0 | 23010 | 60.27 | 97.11 | 300 | 300 | 0 | 0 | 0 | 0 |