The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_AUFBVLIA logic in the Incremental Track. Chart
Results were generated on 2026-07-25
Benchmarks: 300
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|
| Yices2 | - | - | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 552 | 6611.27 | 6610.27 | 0 | 300 | 0 | 4 | 0 |
| SMTInterpol | 0 | 522 | 73302.72 | 72005.33 | 0 | 300 | 0 | 34 | 0 |
| cvc5 | 0 | 509 | 70854.26 | 70843.36 | 0 | 300 | 0 | 46 | 1 |
| z3-BooledASS ne | 0 | 0 (base +0) | 1.78 | 2.27 | 0 | 300 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 300 | 0 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 525 | 701.17 | 701.17 | 0 | 284 | 16 | 0 | 0 |
| cvc5 | 0 | 308 | 790.10 | 790.10 | 0 | 172 | 128 | 0 | 0 |
| SMTInterpol | 0 | 301 | 1028.15 | 1028.15 | 0 | 164 | 136 | 0 | 0 |
| z3-BooledASS ne | 0 | 0 (base +0) | 1.78 | 2.27 | 0 | 300 | 0 | 0 | 0 |
| z3-BooledASS-base n | 0 | 0 | 0.00 | 0.00 | 0 | 300 | 0 | 0 | 0 |