The International Satisfiability Modulo Theories (SMT) Competition.
Competition results for the QF_AUFBV logic in the Single Query Track. Chart
Results were generated on 2026-07-25
Benchmarks: 75
Time Limit: 1200 seconds
Memory Limit: 30720 GB
| Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24 seconds Performance (parallel) |
|---|---|---|---|---|
| Bitwuzla | Bitwuzla | Bitwuzla | Bitwuzla | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Bitwuzla | 0 | 65 | 1606.92 | 1615.30 | 65 | 25 | 40 | 10 | 0 | 10 | 0 |
| bitwuzla-dandelion n | 0 | 65 (base +0) | 2745.11 | 2753.55 | 65 | 25 | 40 | 10 | 0 | 10 | 0 |
| Yices2 | 0 | 60 | 2646.53 | 2654.22 | 60 | 21 | 39 | 15 | 0 | 15 | 0 |
| cvc5-cvc5-xyz ne | 0 | 45 (base +0) | 946.99 | 952.54 | 45 | 13 | 32 | 30 | 0 | 30 | 0 |
| cvc5 | 0 | 45 | 950.39 | 956.02 | 45 | 13 | 32 | 30 | 0 | 30 | 0 |
| z3-BooledASS ne | 0 | 36 (base -20) | 3422.63 | 3427.39 | 36 | 11 | 25 | 39 | 0 | 19 | 0 |
| SMTInterpol | 0 | 30 | 1300.19 | 1080.49 | 30 | 4 | 26 | 45 | 0 | 32 | 0 |
| bitwuzla-dandelion-base n | 0 | 65 | 1883.35 | 1891.67 | 65 | 25 | 40 | 10 | 0 | 10 | 0 |
| z3-BooledASS-base n | 0 | 56 | 3659.75 | 3667.08 | 56 | 15 | 41 | 19 | 0 | 19 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 45 | 959.68 | 965.32 | 45 | 13 | 32 | 30 | 0 | 30 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Bitwuzla | 0 | 65 | 1606.92 | 1615.30 | 65 | 25 | 40 | 10 | 0 | 10 | 0 |
| bitwuzla-dandelion n | 0 | 65 (base +0) | 2745.11 | 2753.55 | 65 | 25 | 40 | 10 | 0 | 10 | 0 |
| Yices2 | 0 | 60 | 2646.53 | 2654.22 | 60 | 21 | 39 | 15 | 0 | 15 | 0 |
| cvc5-cvc5-xyz ne | 0 | 45 (base +0) | 946.99 | 952.54 | 45 | 13 | 32 | 30 | 0 | 30 | 0 |
| cvc5 | 0 | 45 | 950.39 | 956.02 | 45 | 13 | 32 | 30 | 0 | 30 | 0 |
| z3-BooledASS ne | 0 | 36 (base -20) | 3422.63 | 3427.39 | 36 | 11 | 25 | 39 | 0 | 19 | 0 |
| SMTInterpol | 0 | 30 | 1300.19 | 1080.49 | 30 | 4 | 26 | 45 | 0 | 32 | 0 |
| bitwuzla-dandelion-base n | 0 | 65 | 1883.35 | 1891.67 | 65 | 25 | 40 | 10 | 0 | 10 | 0 |
| z3-BooledASS-base n | 0 | 56 | 3659.75 | 3667.08 | 56 | 15 | 41 | 19 | 0 | 19 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 45 | 959.68 | 965.32 | 45 | 13 | 32 | 30 | 0 | 30 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Bitwuzla | 0 | 25 | 1177.99 | 1181.34 | 25 | 25 | 0 | 0 | 50 | 0 | 0 |
| bitwuzla-dandelion n | 0 | 25 (base +0) | 1546.45 | 1549.78 | 25 | 25 | 0 | 0 | 50 | 0 | 0 |
| Yices2 | 0 | 21 | 2307.47 | 2310.30 | 21 | 21 | 0 | 4 | 50 | 4 | 0 |
| cvc5-cvc5-xyz ne | 0 | 13 (base +0) | 407.30 | 408.91 | 13 | 13 | 0 | 12 | 50 | 12 | 0 |
| cvc5 | 0 | 13 | 419.16 | 420.82 | 13 | 13 | 0 | 12 | 50 | 12 | 0 |
| z3-BooledASS ne | 0 | 11 (base -4) | 1558.26 | 1559.75 | 11 | 11 | 0 | 14 | 50 | 10 | 0 |
| SMTInterpol | 0 | 4 | 990.13 | 915.54 | 4 | 4 | 0 | 21 | 50 | 14 | 0 |
| bitwuzla-dandelion-base n | 0 | 25 | 917.11 | 920.37 | 25 | 25 | 0 | 0 | 50 | 0 | 0 |
| z3-BooledASS-base n | 0 | 15 | 1748.91 | 1750.97 | 15 | 15 | 0 | 10 | 50 | 10 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 13 | 413.84 | 415.47 | 13 | 13 | 0 | 12 | 50 | 12 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Bitwuzla | 0 | 40 | 428.93 | 433.96 | 40 | 0 | 40 | 6 | 29 | 6 | 0 |
| bitwuzla-dandelion n | 0 | 40 (base +0) | 1198.67 | 1203.78 | 40 | 0 | 40 | 6 | 29 | 6 | 0 |
| Yices2 | 0 | 39 | 339.06 | 343.92 | 39 | 0 | 39 | 7 | 29 | 7 | 0 |
| cvc5 | 0 | 32 | 531.23 | 535.20 | 32 | 0 | 32 | 14 | 29 | 14 | 0 |
| cvc5-cvc5-xyz ne | 0 | 32 (base +0) | 539.69 | 543.63 | 32 | 0 | 32 | 14 | 29 | 14 | 0 |
| SMTInterpol | 0 | 26 | 310.06 | 164.96 | 26 | 0 | 26 | 20 | 29 | 18 | 0 |
| z3-BooledASS ne | 0 | 25 (base -16) | 1864.37 | 1867.64 | 25 | 0 | 25 | 21 | 29 | 5 | 0 |
| z3-BooledASS-base n | 0 | 41 | 1910.84 | 1916.11 | 41 | 0 | 41 | 5 | 29 | 5 | 0 |
| bitwuzla-dandelion-base n | 0 | 40 | 966.24 | 971.30 | 40 | 0 | 40 | 6 | 29 | 6 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 32 | 545.84 | 549.84 | 32 | 0 | 32 | 14 | 29 | 14 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Yices2 | 0 | 53 | 42.45 | 49.01 | 53 | 16 | 37 | 0 | 22 | 0 | 0 |
| Bitwuzla | 0 | 51 | 75.24 | 81.58 | 51 | 15 | 36 | 0 | 24 | 0 | 0 |
| bitwuzla-dandelion n | 0 | 49 (base -3) | 116.72 | 122.78 | 49 | 14 | 35 | 0 | 26 | 0 | 0 |
| cvc5-cvc5-xyz ne | 0 | 42 (base +0) | 77.33 | 82.44 | 42 | 11 | 31 | 0 | 33 | 0 | 0 |
| cvc5 | 0 | 42 | 77.40 | 82.56 | 42 | 11 | 31 | 0 | 33 | 0 | 0 |
| z3-BooledASS ne | 0 | 27 (base -17) | 63.81 | 67.14 | 27 | 8 | 19 | 18 | 30 | 0 | 0 |
| SMTInterpol | 0 | 27 | 198.71 | 74.08 | 27 | 2 | 25 | 6 | 42 | 0 | 0 |
| bitwuzla-dandelion-base n | 0 | 52 | 109.59 | 116.08 | 52 | 16 | 36 | 0 | 23 | 0 | 0 |
| z3-BooledASS-base n | 0 | 44 | 50.94 | 56.34 | 44 | 10 | 34 | 0 | 31 | 0 | 0 |
| cvc5-cvc5-xyz-base n | 0 | 42 | 77.58 | 82.78 | 42 | 11 | 31 | 0 | 33 | 0 | 0 |